发表于 经过vip亚博 -暂无评论on Linux 5.10 LTS release – Main changes, Arm, MIPS and RISC-V architectures

Linux 5.10 LTS release – Main changes, Arm, MIPS and RISC-V architectures

Linux 5.10 release

Linus Torvalds has just released Linux 5.10: Ok, here it is – 5.10 is tagged and pushed out. I pretty much always wish that the last week was even calmer than it was, and that’s true here too. There’s a fair amount of fixes in here, including a few last-minute reverts for things that didn’t get fixed, but nothing makes me go “we need another week”. Things look fairly normal. It’s mostly drivers – as it should be – with a smattering of fixes all over: networking, architectures, filesystems, tooling.. The shortlog is appended, and scanning it gives a good idea of what kind of things are there. Nothing that looks scary: most of the patches are very small, and the biggest one is fixing pin mapping definitions for a pincontrol driver. This also obviously means that the merge window for 5.11 will start tomorrow. I already have a couple […]

发表于 经过vip亚博 -10 Commentson Linux 5.9 Release – Main Changes, Arm, MIPS & RISC-V Architectures

Linux 5.9版本 - 主要变化，ARM，MIPS和RISC-V架构

Linux 5.9 release

Linus Torvalds has just announced the release of Linux 5.9 on lkml: Ok, so I’ll be honest – I had hoped for quite a bit fewer changes this last week, but at the same time there doesn’t really seem to be anything particularly scary in here. It’s just more commits and more lines changed than I would have wished for. The bulk of this is the networking fixes that I already mentioned as being pending in the rc8 release notes last weekend. In fact, about half the patch (and probably more of the number of commits) is from the networking stuff (both drivers and elsewhere). Outside of that, the most visible thing is a reinstatement of the fbdev amba-clcd driver – that’s a noticeable patch, but it’s basically just mainly a revert. The rest is really really tiny (mostly some other minor driver updates, but some filesystem and architecture fixes […]

发表于 经过vip亚博 -7条评论on Linux 5.8 Release – Main Changes, Arm, MIPS, and RISC-V Architectures

Linux 5.8发行– Main Changes, Arm, MIPS, and RISC-V Architectures

Linux 5.8发行

Linus Torvalds has just released Linux 5.8: So I considered making an rc8 all the way to the last minute, but decided it’s not just worth waiting another week when there aren’t any big looming worries around. Because despite the merge window having been very large, there really hasn’t been anything scary going on in the release candidates. Yeah, we had some annoying noise with header file dependencies this week, but that’s not a new annoyance, and it’s also not the kind of subtle bug that keeps me up at night worrying about it. It did reinforce how nice it would be if we had some kind of tooling support to break nasty header file dependencies automatically, but if wishes were horses.. Maybe some day we’ll have some kind of SAT-solver for symbol dependencies that can handle all our different architectures and configurations, but right now it’s just a manual […]

发表于 经过vip亚博 -21 Commentson Ingenic X2000 IoT Application Processor Combines 32-bit MIPS Xburst 2 Cores with Xburst 0 Real-time Core

Ingenic X2000IoT Application Processor Combines 32-bit MIPS Xburst 2 Cores with Xburst 0 Real-time Core

Ingenic X2000

在手臂的世界,异构处理器pretty common, with for example big.LITTLE / dynamIQ application processors mixing powerful Cortex-A7x cores with power-efficient Cortex-A5x cores., or “industrial” processor such NXP i.MX 8M family with Cortex-A53 application cores combined with Cortex-M4F real-time core. Maybe I did not follow enough, but I hadn’t really seen anything equivalent in MIPS world, except if we count Ingenic T31 with RISC-V and MIPS cores. That is until today where I was informed about documents related to Ingenic X2000 IoT application processor with two 32-bit MIPS Xburst 2 core, one MIPS Xburst 0 real-time cores, as well as up to 256MB RAM built-into the SoC. Ingenic X2000 specifications: CPU Core – Dual XBurst 2, MIPS ISA based, frequency up to 1.5 GHz with 32KB L1 x2 Cache, 512KB L2 Cache, 32KB SRAM, FPU,128bit SIMD MCU Core – XBurst 0 MIPS core @ 300MHz for security and real-time […]

发表于 经过vip亚博 -1条评论on Linux 5.7 Released – Main Changes, Arm, MIPS and RISC-V Architectures

Linux 5.7 Released – Main Changes, Arm, MIPS and RISC-V Architectures

Linux 5.7 ChangElog

好吧……我有点晚了。Linus Torvalds上周发布了Linux 5.7：因此，我们上周保持了一个相当平静的态度，没有什么真正尖叫的“让我们延迟再延迟RC”。敲门木 - 我们希望这次我们没有任何愚蠢的潜伏，就像我们在5.6中的最后一刻的wifi回归一样。但是，尽管上一次令人尴尬的回归，但一切看起来都很好。而且，我看过上一两周的大多数讨论都是关于即将到来的功能的，因此合并窗口现在已经打开，我明天将像往常一样开始处理拉的请求。亚博体育官下载但是与此同时，请给这个旋转。We’ve got a lot of changes in 5.7 as usual (all the stats look normal – but “normal” for us obviously pretty big and means “almost 14 thousand non-merge commits all over, from close to two thousand developers”), So the appended shortlog is only […]

发表于 经过vip亚博 -2条评论on QEMU 5.0 Supports Recent Armv8.x Features, Cortex-M7 CPU, Host Directory Access, and More

QEMU 5.0 Supports Recent Armv8.x Features, Cortex-M7 CPU, Host Directory Access, and More

Qemu 5.0

Qemu（快速模拟器）是一个开源仿真器，非常适合在不拥有适当的硬件时在ARM，RISC-V等各种架构上运行各种架构的程序。开发人员现在发布了QEMU 5.0.0将有很多新功能，例如对ARMV8.4架构的支持，ARMV8.4架构，ARM Cortex-M7处理器，MIPS，POWERPC，RISC-V，S390的各种更改，S390…建筑，支持，支持，支持使用virtiofsd等等，从访客中访问主机文件系统上的目录。有232名开发人员的2800多个提交人，因此在此处编写的更改清单列表，但其中一些亮点包括：通过virtiofsd支持将主机文件系统目录传递给访客，通过armv8.1 vhe/vmid16/pan支持访客。/pmu，ARMV8.2 UAO/DCPOP/ATS1E1/TTCNP，ARMV8.3 RCPC/CCIDX，ARMV8.4 PMU/RCPC添加了ARM Cortex-M7 CPU支持新ARM ARP板：Tacoma-BMC，NetDuino Plus 2和Orange Pi PC，Allwinner SOC模型现在启动USB端口TPM支持[…]

发表于 经过vip亚博 -8条评论在Ingenic T31 AI视频处理器上结合了MIPS和RISC-V核心

Ingenic T31 AI Video Processor Combines MIPS & RISC-V Cores

Ingenic T31 MIPS和RISC-V视频处理器

Last week we asked “is MIPS dead?” question following the news that Wave Computing had filed for bankruptcy, two MIPS Linux maintainers had left, and China-based CIP United now obtained the exclusive MIPS license rights for mainland China, Hong Kong, and Macau. Ingenic is one of those Chinese companies that have offered MIPS-based processors for several years, but one commenter noted that Ingenic joined the RISC-V foundation, and as a result, we could speculate the company might soon launch RISC-V processors, potentially replacing their MIPS offerings. But Ingenic T31 video processor just features both with a traditional Xburst MIPS Core combines with a RISC-V “Lite” core Ingenic T31 specifications: Processors XBurst 1 32-bit MIPS core clocked at 1.5GHz with Vector Deep Learning accelerator based on SIMD128, 64KB + 128KB L1/L2 Cache RISC-V independent lite core System Memory – Built-in 512Mbit (64MB) or 1Gbit (128MB) DDR2 Storage – Quad SPI flash, […]

发表于 经过vip亚博 -12个评论on Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More…

Is MIPS Dead? Lawsuit, Bankruptcy, Maintainers Leaving and More…

MIPS Dead

When in 2018, Blu posted a guest post entitled “Baikal T1 MIPS Processor – The Last of the Mohicans?” I thought maybe it was too pessimistic with regard to the future of MIPS architecture. At the time, MIPS belonged to Imagination Technologies, but soon the company had its own financial problems and had to sell MIPS assets to Wave Computing. The latter eventually announced the launch of MIPS Open Initiative early last year, so there was some hope as interest might pick up to compete against RISC-V and Arm again. But in recent months, MIPS related news has not been so good. First, Wave Computing decided to end MIPS Open Initiative in November 2019, then Paul Burton and Ralf Baechle removed themselves from the Linux kernel MIPS maintainer list in February 2020, as their work with MIPS ended leaving Thomas Bogendoerfer as the only maintainer. But this month, things turned […]